The present invention relates to a method of fabricating a gate electrode, and particularly, to a method of fabricating gate electrodes of a NMOS and a PMOS which are used to complementary metal oxide semiconductor (CMOS) device.
Generally, a CMOS is a kind of semiconductor device, which consists of a NMOS and a PMOS transistor. The gate electrodes of a NMOS and a PMOS each are formed from a material like polysilicon, silicide and polycide. The material, which forms the gate electrode, severely affects the characteristics of the CMOS device. Therefore, polycide, which has excellent electrical conductivity and stability, is mainly employed to the gate electrode.
FIG. 1 is a cross-sectional view of conventional gate electrodes of a NMOS and a PMOS transistor of a CMOS device. In this figure, reference number 1 denotes a silicon substrate, 2 a N-well, 3 a P-well, 4 a field oxide, 5 a gate oxide, 6 a polysilicon layer and 7 a silicide layer, respectively.
As shown in FIG. 1, a conventional CMOS device has a twin-tub structure. The gate electrode of this CMOS device is formed by the following process. First, the N-well 2 the and the P-well 3, having a twin-tub structure, are formed in a predetermined portion of the silicon substrate 1, and the field oxide 4 is formed on a predetermined portion of the N-well 2 and the P-well 3. Then, the gate oxide 5, the polysilicon layer 6 and the silicide layer 7 are sequentially formed on the overall surface of the substrate, and the stacks of the silicide layer, the polysilicon layer and the gate oxide are patterned to form polycide (polysilicon+silicide) gate electrodes 6 and 7.
In the conventional method for fabricating the gate electrode as described above, each gate electrode of the NMOS and the PMOS is formed of the same polycide.
However, the conventional method, in which gate electrodes of NMOS and PMOS each is formed of the same polycide, involves the following problems. That is, the silicide layer produces stress in large quantities and impurities contained in the silicide layer transfer into the gate oxide, deteriorating the characteristics of the gate oxide. This decreases the reliability and yield of the CMOS device.
It is an object of the present invention to provide a method for fabricating a gate electrode of a CMOS, in which each gate electrode of a NMOS and a PMOS is formed of polysilicon and polycide, respectively, so that the deterioration of the device caused by the silicide lager and stress is reduced, therefore, improving the reliability and yield of the CMOS device.
To accomplish the object of the present invention, there is provided a method for fabricating a gate electrode of a CMOS device, comprising the steps of: sequentially forming a gate insulating layer, a first conductive layer and a protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.